1. Field of the Invention
The present invention relates to memory devices, and more particularly relates to an interconnection network for connecting data and reference cells to sense amplifiers in a memory device.
2. Description of the Related Art
Dynamic random access memory (DRAM) is one type of semiconductor memory device which has been and is widely used. DRAMs are volatile. EEPROM (Electrically Erasable and Programmable Read Only Memory) is another type of semiconductor memory device which is not volatile. A disadvantage of EEPROM is its lower speed in read/write operation as compared to DRAMs.
Owing to recent advances in magnetic materials, magnetic random access memory (MRAM) has been developed as one of non-volatile memory devices which is capable of higher speed operations, especially in the read process. An MRAM device typically includes a plurality of memory cells arrayed on intersections of word lines and bit lines. Each cell of a MRAM device may be a type of magnetic tunnel junction (MTJ), which has two magnetic layers separated by an insulating layer. Data stored in memory cells of MTJ type may be represented as a direction of magnetic vectors in the magnetic layers, and the memory cells can hold the stored data until the direction of magnetic vectors is changed by signals externally applied to the memory cells. A typical MRAM array of MTJ type is described in the article entitled "A 10 ns Read Write Non-Volatile Memory Array using a Magnetic Tunnel Junction and FET Switch in Each Cell" by Roy Scheuerlein, et al., pp. 128-129, ISSCC 2000.
It is well known that, in high density memory devices, asymmetric network affects sense amplifiers in a memory device, which are used to detect states of memory cells each having a logic state "0" or "1", or a state of similar magnitude. For example, noise sources can be unequally coupled to an asymmetric network connecting memory cells to sense amplifiers, thereby causing delay and/or disruption of signals being sensed in the amplifiers. In a dynamic sensing system, asymmetry in an interconnection network between sense amplifiers and memory array causes differences in load capacitance at the inputs of a sense amplifier. Such load capacitance difference in turn causes a delay in a transition of the sense amplifier either from "1" to "0" or from "0" to "1" (here, "0" and "1" are logic values). Thus, asymmetry in an interconnection network affects sensing speed of sense amplifiers. In an asymmetric interconnection network, the sensing of a valid state in a sense amplifier may also be degraded by coupling events from sources such as the substrate or neighboring metallic wires. An example of an asymmetric network is described in the article entitled "Non-Volatile RAM based on Magnetic Tunnel Junction Elements" by M. Durlam, et al., pp. 130-131, ISSCC 2000.
Thus, a need exists for a process for minimizing asymmetry in an interconnection network between memory cells and sense amplifiers in a memory device.